1. Field of the Invention
The present invention relates to a solid-state imaging device and a method of manufacturing such a solid-state imaging device, and also relates to an electronic apparatus including the solid-state imaging device.
2. Description of the Related Art
Solid-state imaging devices can be generally classified into those of an amplification-type typified by CMOS (Complementary Metal Oxide Semiconductor) image sensor and those of a charge-transfer type typified by CCD (Charge Coupled Device) image sensors. These solid-state imaging devices have been widely used for digital still cameras, digital video cameras, and so on. Furthermore, in recent years, CMOS image sensors have mainly been used for solid-state imaging devices mounted on mobile devices such as camera cell-phones and PDAs (Personal Digital Assistants) because of their low power voltages, low power consumption, and so on.
The CMOS solid-state imaging device includes a silicided peripheral circuit section and a silicide-free pixel section. In other words, for CMOS transistors in the peripheral circuit section, a metal silicide layer is formed on both the surface of a polysilicon gate electrode and the surface a source/drain region to attain a decrease in resistance. On the other hand, the pixel section is not silicided so as to prevent an adverse influence of electrons generated from a metal silicide layer. The metal silicide layer has many fixed electrons. When these electrons of the layer leak into a photodiode provided as a photoelectric conversion element, dark current is caused to degrade image quality. Therefore, the pixel section is prevented from being silicided. In general, a silicide blocking layer is employed to protect the pixel section when the peripheral circuit section is silicided. Covering the pixel section with the silicide blocking layer is disclosed in, for example, Japanese Unexamined Patent Application Publication No. 2005-223085 and Japanese Unexamined Patent Application Publication No. 2005-260077.
FIG. 1 and FIG. 2 are schematic diagrams that illustrate main parts of a pixel section and a peripheral circuit section of the related-art CMOS solid-state imaging device. As shown in FIG. 1, a solid-imaging device 101 includes a pixel section 103 and a peripheral circuit section 104 on a semiconductor substrate 102. The pixel section 103 includes a plurality of pixels arranged on the semiconductor substrate 102. The peripheral circuit section 104 includes a logic circuit or the like formed around the pixel section 23. The pixel section 103 includes an isolation portion 121 constructed of a first conductivity type semiconductor layer 122 and an insulating layer (e.g., a silicon dioxide layer) 123 formed thereon. In addition, the pixel section 103 also includes a plurality of pixels 110 each constructed of a photodiode (PD) 107 provided as a photoelectric conversion element and a plurality of pixel transistors 108. Here, the pixels 110 are arranged in a matrix in a plane and are separated from one another by the isolation portions 121. In FIG. 1, only one of pixel transistors 108 is represented on behalf of all of them. The pixel transistor 108 includes a source/drain region 109, a gate insulating film (not shown), and a gate electrode (not shown).
A silicide blocking layer 111, such as a silicon nitride film, is applied to the upper part of the pixel 110 and covers the entire pixel section 103 to be protected from the influence when the CMOS transistors in the peripheral circuit section 104 is silicided as described later (see FIG. 1 and FIG. 2). A plurality of wiring layers 114 are formed above the silicide blocking layer 111. The layers 114 include a plurality of wiring lines 113 stacked with an insulating interlayer 112 in between. Furthermore, an on-chip color filter 115 and an on-chip microlens 116 are formed above the insulating interlayer 112. FIG. 2 shows a unit pixel including a photodiode (PD) 107 and three pixel transistors, i.e., a transfer transistor Tr1, a reset transistor Tr2, and an amplification transistor Tr3. The transfer transistor Tr1 includes a source/drain region 1091, which becomes a floating diffusion (FD) region with the photodiode 107, and a transfer gate electrode 161. The reset transistor Tr2 includes a pair of source/drain regions 1091 and 1092 and a reset gate electrode 162. The amplification transistor Tr3 includes a pair of source/drain region 1092 and 1093 and an amplification gate electrode 163.
In the peripheral circuit section 104, for example, there is formed an isolation portion 125 with a STI (Shallow Trench Isolation) structure obtained by filling a groove 126 of the semiconductor substrate 102 with an insulating layer 127 such as a silicon dioxide layer. A plurality of CMOS transistors 130 are formed including an n-channel MOS transistor 128 and a p-channel MOS transistor 129 separated from each other by the isolation portion 125. The n-channel MOS transistor 128 includes a pair of n-type source/drain regions 133 and 134 which are formed in a p-type semiconductor well region 132, and a gate electrode (e.g., a polysilicon film) 136 with a gate insulating film 135 in between. The p-channel MOS transistor 129 includes a pair of p-type source/drain regions 143 and 144 which are formed in an n-type semiconductor well region 142, and a gate electrode (e.g., a polysilicon film) 146 with a gate insulating film 135 in between. Sidewalls (sidewall layers) 151, which are insulating layers, are formed on the side walls of the respective gate electrodes 136 and 146. The n-channel MOS transistor 128 includes source/drain regions 133 and 134. Also, the p-channel MOS transistor 129 includes source/drain regions 143 and 144. Each of the source/drain regions 133, 134, 143, and 144 includes a highly-doped region and a lightly-doped region, having a so-called LDD structure.
In addition, the n-channel MOS transistor 128 and the p-channel MOS transistor 129 formed in the peripheral circuit section 104 are metal-silicided, respectively. In other words, a metal silicide layer 152, such as a Co silicide layer, is formed on each of the surfaces of the respective source/drain regions 133, 134, 143, and 144 in addition to the surfaces of the respective gate electrodes 136 and 146.